Twofold State Assignment for the Moore Finite State Machines

A method is proposed for reducing the hardware expenditure in the circuits of the Moore finite-state machines (FSMs) implemented in the EMB and LUT basis. The method is based on splitting a set of states into classes, with each of them corresponding to one block of logic elements. Moreover, each state has two codes. This approach leads to the three-level circuit of the Moore FSM. An example of the Moore FSM synthesis using the proposed method and the application conditions for this method are considered. Studies based on the standard benchmark FSMs have shown that the proposed method reduces the hardware expenditure compared to the other known solutions.